1. Field of the Invention
The present invention relates to an electrophoretic display (EPD) device, and more particularly, to an EPD device capable of delaying or preventing a sealant from leaking down by forming a dam pattern prior to a sealing process using the sealant, and a method for fabricating the same.
2. Description of the Background Art
Generally, an electrophoretic display (EPD) device is a display device using a principle that colloidal particles move to one polarity when one pair of electrodes to which a voltage is applied are immersed into colloidal solution. The EPD device does not use a backlight, but implements a wide viewing angle, high reflectivity, high readability, low power consumption, etc., thereby being anticipated as electronic paper.
The EPD device has a structure in which an electrophoretic substance is interposed between two electrodes, and at least one of the two electrodes is transparent to display images.
When a potential is applied onto the two electrodes, charged particles in the electrophoretic substance move to one electrode or another electrode. This allows images to be observed through a viewing sheet or an opposite electrode.
The structure of the EPD device will be explained in more detail with reference to FIGS. 1 and 2.
FIG. 1 is a schematic planar view of an electrophoretic display (EPD) device in accordance with the conventional art, and FIG. 2 is a schematic sectional view of the electrophoretic display (EPD) of FIG. 1, which is taken along line ‘II-II’ of FIG. 2.
As shown in FIGS. 1 and 2, the conventional EPD device comprises: a lower substrate 51 having a plurality of gate lines and data lines (not shown) crossing each other, a pixel electrode 67, and a thin film transistor (TFT) to electrically connect the gate lines to the pixel electrode 67; an upper substrate 75 having a common electrode 73 facing the pixel electrode 67 and generating an electric field; a display layer 71 formed between the lower substrate 51 and the upper substrate 75; and a seal pattern 77 for sealing each outer circumferential surface of the lower substrate 51, the upper substrate 75, and the display layer 71.
As shown in FIG. 2, on the lower substrate 51, formed are a plurality of gate lines (not shown) in a horizontal direction, and a gate electrode 53 extending from the gate lines.
A gate insulating film 55 and a semiconductor layer 57 are sequentially formed on the lower substrate 51 including the gate electrode 53 and the gate lines (not shown).
A resistive contact member doped with ‘n’ type impurities with high concentration, an ohmic contact layer 59 is formed on the semiconductor layer 57. Here, the ohmic contact layer 59 is formed on the semiconductor layer 57 at both sides of the gate electrode 53.
On the ohmic contact layer 59 and the gate insulating film 55, formed are a plurality of data lines (not shown), a source electrode 61 extending from the data lines, and a drain electrode 63 of the TFT.
On the source electrode 61, the drain electrode 63, the semiconductor layer 57, and the gate insulating film 55, formed is a passivation film 65 composed of a low dielectric insulating material having an excellent planarization characteristic.
At the passivation film 65, formed are a contact hole 67 that exposes the drain electrode 63, and a pixel electrode 69 electrically connected to the drain electrode 63.
The display layer 71 is provided with a plurality of electrophoretic substances 71a including electronic ink having pigment particles. The pigment particles are represented as black and white, and are charged positively and negatively, respectively.
The common electrode 73 formed of a transparent conductive material is formed on an entire surface of the display layer 71, thereby forming an electric field to drive pigment particles charged positively and negatively with facing the pixel electrode 67.
The upper substrate 75 formed of glass or plastic, etc. is laminated on the common electrode 73. Here, the upper substrate 75 is laminated on the lower substrate 51 through a laminator, and then is bonded onto the lower substrate 51 by an adhesive.
The seal pattern 77 is formed by a sealing process with a sealant on each outer circumferential surface of the lower substrate 51, the upper substrate 75, and the display layer 71 interposed between the two substrates. More specifically, once a sealant is dispensed between the upper substrate 75 and the display layer 71, the sealant is filled therebetween by a tensile force thereby to form the seal pattern 77.
In the conventional EPD device, a voltage is applied to the two facing electrodes 67 and 73 to generate a potential difference on both of the electrodes. Thus, the charged pigment particles of black and white are moved to the electrodes having different polarities so as to display images. Accordingly, an observer (not shown) can view images of black and white.
However, the conventional EPD device is fabricated with the following difficulties at the time of dispensing a sealant.
Referring to FIG. 1, a sealant 77a is dispensed on each outer circumferential surface of the lower substrate 51, the upper substrate 75, and the display layer 71 interposed between the two substrates. The dispensed sealant 77a serves to form the seal pattern 77 through a sealing process. However, as times lapses after the sealant 77a is dispensed, the sealant 77a flows up to undesired regions. This may cause unnecessary process margins at the time of subsequent processes.
Particularly, a part of the sealant 77a occupies a part of a bonding region of a driving circuit, which causes the driving circuit to be bonded to the lower substrate with difficulty, and a display panel to be discarded.
Furthermore, while the sealant having been dispensed to a part of the display panel is filled between the upper substrate and the display layer by a tensile force, the sealant continues to flow to a reverse direction, i.e., outside of the display panel, the bonding region of the driving circuit.
As shown in FIG. 1, in the case that a part of the sealant 77a flows in a reverse direction (i.e., a part of the sealant 77a is separated from the seal pattern at each edge and each corner of the EPD device), sealant inferiority occurs due to interference between a flexible printed circuit (FPC) and the driving circuit. As the sealant flows to unnecessary regions, the entire usage amount of the sealant is increased at the time of forming the seal pattern.
In order to obtain a sealant margin, the size of the display panel has to be increased, or an active region has to be decreased. This decreased active region may cause a design margin to be decreased.
Furthermore, since a large amount of sealant is required at the time of a sealant dispensing process, a sealant discharge time is increased to increase the entire process time. This may degrade the productivity and require additional installations.